# Design Rule Verification Report

Date: |  | 9/19/2022
Time: |  | 11:43:58 AM
Elapsed Time: |  | 00:00:02
Filename: |  | C:\Users\marka\Fall-2022\Junior-Design\555-timer-PWM-fan\PCB\pcb.PcbDoc
Warnings: |  | 0
Rule Violations: |  | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=8mil) (OnLayer('Top Layer')),(All) | 0
Clearance Constraint (Gap=7.874mil) (All),(All) | 0
Clearance Constraint (Gap=8mil) (OnLayer('Bottom Layer')),(All) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Modified Polygon (Allow modified: No), (Allow shelved: No) | 0
Width Constraint (Min=15mil) (Max=100mil) (Preferred=30mil) (All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) | 0
Minimum Annular Ring (Minimum=3mil) (All) | 0
Hole Size Constraint (Min=7.874mil) (Max=248.031mil) (All) | 0
Hole To Hole Clearance (Gap=10mil) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) | 0
Silk To Solder Mask (Clearance=3.937mil) (IsPad),(All) | 0
Silk to Silk (Clearance=3.937mil) (All),(All) | 0
Net Antennae (Tolerance=0mil) (All) | 0
Board Clearance Constraint (Gap=0mil) (All) | 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) | 0
Total | 0